1. Field
The following description relates to an apparatus and method for non-blocking execution of a static scheduled processor that may maintain an operation ability without switching the entire processor to a stall state for a long cycle when a latency greater than an expected latency occurs during an operation with respect to input data.
2. Description of the Related Art
A static scheduled processor refers to a processor which determines an order in which and a functional unit (FU) by which an operation to be applied to input data is to be executed, when compiling. Among software pipelining algorithms, a Samsung Reconfigurable Processor (SRP), which determines a schedule, may correspond to the static scheduled processor.
An operation schedule of a processor may be generated for an operation to produce an optimal execution performance, in view of an available FU, a point in time at which input data for the operation is prepared, and a latency of the operation, for example.
Here, computation of an accurate timing for a regular latency operation, more particularly, an operation of which a latency is regular, may be possible when compiling, and thus, an optimal schedule may be generated. However, in a case of an irregular latency operation, more particularly, when an operation of which a latency is irregular, a method of generating a schedule by assuming a single latency value when compiling, and handling an occurrence of a latency differing from the assumed latency at a runtime may be employed.